1. Technical Field
The invention relates generally to electrical computers and data processing systems (Class 364), and more particularly to instruction prefetch and interrupt (Subclasses 263.1 and 263.2). In even greater particularity, the invention relates to exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception.
2. Related Art
Instruction prefetch is commonly used in microprocessors to optimize computer execution time. Instructions prefetched from main memory or cache are stored in an instruction prefetch queue for input to the instruction decoder.
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: exception handling for prefetched instructions.
Computer architectures commonly use exceptions to signal the detection of an error condition before, during or after execution of an instruction. Exception logic monitors each instruction retrieved from memory to determine whether an exception should be signaled, and stores the addresses of those instruction bytes that may potentially cause an exception. Each exception has associated with it a vector used to locate a corresponding exception handling routine.
In response to the execution of an instruction that causes an exception, program execution is interrupted, and the computer system vectors to a corresponding exception handling routine. Exceptions may be categorized based on how the exception is reported, and how the associated exception handling routine returns to the program: (a) faults are reported for the next instruction, and the return is to the faulting instruction which is reexecuted, (b) traps are reported immediately after the execution of the instruction that caused the exception, and the return is to the instruction after the instruction that caused the trap, and (c) aborts occur as a result of system errors, and generally require restart.
For example, in the case of the 386 architecture, exceptions that may be asserted include: Debug, Invalid Op code, Coprocessor Extension Not Available, Coprocessor Error, Stack Fault, Page Fault, Segment Not Present, and Limit Violation.
Instruction prefetch speculatively fills the prefetch queue with instruction bytes that, because of changes of flow (such as branching), may not actually be executed. Since an exception may be asserted for any of the prefetched instruction bytes, the computer system must implement a technique for identifying instruction bytes in the execution stream that may cause an exception so that the appropriate exception handling routine can be invoked.
One exception handling technique is to include an exception bit with each instruction byte placed in the prefetch queue--if an exception condition is detected, prefetch logic sets the exception bit for the associated instruction byte placed in the prefetch queue. The decoder includes logic for testing the exception bit for each instruction byte decoded for execution, and for invoking the appropriate exception handling routine. This technique is disadvantageous in that it adds to decoder complexity by requiring it to implement exception handling.
Another exception handling technique is to keep track of the address of the instruction being currently decoded for execution. Exception logic compares each instruction address with those addresses identified as potentially causing an exception--if a match is detected, the appropriate exception handling routine is invoked. This technique is disadvantageous in that delaying exception detection until after decode means that exception handling will be invoked later in the instruction pipe, requiring instruction execution to be aborted, and related side effects dealt with.
Accordingly, a specific need exists for an improved exception handling technique for prefetched instructions.